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features ? low current consumption: i vdd < 25 a ? rc oscillator ? internal reset during power-up and supply voltage drops (por) ? ?short? trigger window for active mode ? ?long? trigger window for sleep mode ? cyclical wake-up of the microcontroller in sleep mode ? trigger input ? single wake-up input ? reset output ? enable output 1. description the digital window watchdog timer, ATA5021, is designed in atmel ? ?s state-of-the-art 0.8 m soi technology smart-i.s. ? 1. in applications where safety is critical, it is especially important to monitor the microcontroller. normal microcontroller operation is indicated by a cyclically transmitted trigger signal, which is received by a window watchdog timer within a defined time window. a missing or a wrong trigger signal causes the watchdog timer to reset the microcon- troller. the ic is tailored for microcontrollers, which can work in both full-power and sleep mode. with an additional voltage monitoring (power-on reset and supply voltage drop reset), the ata5 021 offers a complete monitori ng solution for micro-systems in automotive and industrial applications. digital window watchdog timer ATA5021 9145d?auto?05/10
2 9145d?auto?05/10 ATA5021 figure 1-1. block diagram with external circuit inp u t s ign a l conditioning o s c por 3 2 power-on re s et 5 mode trigger rc o s cill a tor s t a te m a chine por o s c re s et micro- controller te s t logic 1 w a ke- u p extern a l s witching circ u itry 4 7 en ab le gnd 8 6 c 10 nf r 1 v dd o s c c 1 v dd
3 9145d?auto?05/10 ATA5021 2. pin configuration figure 2-1. pinning so8 5 6 7 8 4 3 2 1 re s et vdd gnd o s c ena mode trig wup table 2-1. pin description pin symbol function 1wup wake-up input (pull-down resistor) there is one digitally debounced wake-up input. during the long watchdog window, each signal slope at the input initiates a reset pulse at pin 5. 2trg trigger input (pull-up resistor) it is connected to the microprocessor?s trigger signal. 3mode mode input (pull-up resistor) the processor?s mode signal initiates the switch over between the long and the short watchdog time. 4ena enable output (push-pull) it is used for the control of perip heral components. it is activated a fter the processor triggers three times correctly. 5 reset reset output (open drain) resets the processor in the case of under-voltage cond ition, a wrong trigger event or if a wake-up event occurs during long watchdog period. 6 vdd supply voltage 7 gnd ground, reference voltage 8 osc rc oscillator
4 9145d?auto?05/10 ATA5021 3. functional description 3.1 supply voltage, pin 6 the ATA5021 requires a st abilized supply voltage v dd = 5v 10% to comply with its electrical characteristics. an external buffer capacitor of c = 10 nf may be connected between pin 6 and gnd. 3.2 rc oscillator, pin 8 the clock frequency, f, can be adjusted by the components r 1 and c 1 according to the formula: with t = 0.18 (c 1 + c board + 0.016) + 0.35 + [1.59 ? (c 1 + c board + 0.016)/85] r 1 (c 1 + c board + 0.016) r 1 (k ) = external resistor at pin 8 c 1 (nf) = external capacitor at pin 8 c board = 0.004 nf; this is the parasitic test board capacity caused by additional wiring on the test assembly. with frequency calculations of original boards, this parasitic capacitor can be omitted. table 3-1. comparison table clock period calculation versus measurement on test board r1 (k )c1 (nf) period ?t? (s) by new formula period ?t? (s) by measurement deviation of new formula versus measurement 10.00 0.23 4.36 4.33 ?0.3% 10.00 0.47 8.20 8.30 1.8% 10.00 1.04 17.26 17.10 1.4% 10.00 4.75 74.40 74.50 1.5% 10.00 10.49 156.30 152.00 ?2.2% 32.91 0.23 13.45 13.25 ?0.4% 32.91 0.47 25.99 26.13 1.9% 32.91 1.04 55.57 55.00 1.2% 32.91 4.75 242.10 241.50 1.2% 32.91 10.49 509.25 505.00 1.6% 46.70 0.23 18.92 18.50 ?1.2% 46.70 0.47 36.69 36.63 0.8% 46.70 1.04 78.63 78.25 1.7% 46.70 4.75 343.03 341.25 0.6% 46.70 10.49 721.70 700.00 ?1.6% 68.00 0.23 27.38 26.75 ?1.4% 68.00 0.47 53.22 53.25 1.4% 68.00 1.04 114.25 112.50 1.5% 68.00 4.75 498.94 497.50 1.2% 68.00 10.49 1049.85 1020.00 0.0% 81.20 0.23 32.61 31.88 ?1.1% f 1 t --- =
5 9145d?auto?05/10 ATA5021 the clock frequency determines all time periods of the logical part as shown in section 7. ?elec- trical characteristics? on page 9 under the subheading ?timing?. 3.3 supply voltage monitoring, pin 5 during ramp-up of the supply voltage and in the case of supply-voltage drops, the integrated power-on reset (por) circuitry sets the internal logic to a defined basic status and generates a reset pulse at the reset output, pin 5. a hysteresis in the por threshold prevents the circuit from oscillating. during ramp-up of th e supply voltage, the reset output stays active for a specified period of time (t 0 ) in order to bring the microcontroller into its defined reset status (see figure 3-1 on page 5 ). 3.4 switch-over mode time, pin 3 the switch-over mode time enables the synchronous operation of microcontroller and watchdog. when the power-on reset time has elapsed, t he watchdog has to be switched to monitoring mode by the microcontroller by a ?low? signal transmitted to the mode pin (pin 3) within the time-out period, t 1 . if the low signal does not occur within t1 (see figure 3-1 on page 5 ), the watchdog generates a reset pulse, t 6 , and t 1 starts again. microcontroller and watchdog are syn- chronized with the swit ch-over mode time, t 1 , each time a reset pulse is generated. figure 3-1. power-on reset and switch-over mode 81.20 0.47 63.47 63.75 1.6% 81.20 1.04 136.32 135.00 1.9% 81.20 4.75 595.56 592.50 0.7% 81.20 10.49 1253.21 1240.00 1.3% 100.00 0.23 40.07 38.88 ?2.1% 100.00 0.47 78.07 78.00 1.2% 100.00 1.04 167.76 164.00 ?1.7% 100.00 4.75 733.17 730.00 0.9% 100.00 10.49 1542.84 1530.00 0.5% 119.50 0.23 47.81 46.38 ?1.7% 119.50 0.47 93.20 93.00 0.8% 119.50 1.04 200.37 200.25 1.1% 119.50 4.75 875.90 870.00 0.5% 119.50 10.49 1843.26 1835.00 0.9% table 3-1. comparison table clock period calculation versus measurement on test board r1 (k )c1 (nf) period ?t? (s) by new formula period ?t? (s) by measurement deviation of new formula versus measurement v dd re s et o u t mode pin 3 pin 5 pin 6 t 0 t 1 t 6
6 9145d?auto?05/10 ATA5021 3.5 microcontroller in active mode 3.5.1 monitoring with the ?short? trigger window after the switch-over mode, the watchdog operates in short watchdog mode and expects a trig- ger pulse from the microcontroller within the defined time window, t 3 , (enable time). the watchdog generates a reset pulse which resets the microcontroller if: ? the trigger pulse duration is too long ? the trigger pulse is within the disable time, t 2 ? there is no trigger pulse figure 3-2 shows the pulse diagram with a missing trigger pulse. figure 3-2. pulse diagram with no trigger pulse during the short watchdog time figure 3-3 shows a correct trigger sequence. the positive edge of the trigger signal starts a new monitoring cycle with the disable time, t 2 . to ensure correct operation of the microcontroller, the watchdog needs to be triggered three times correctly before it sets its enable output. this fea- ture is used to activate or deactivate safety-critical components, which have to be switched to a certain condition (emergency status) in the case of a microcontroller malfunction. as soon as there is an incorrect trigger sequence, the enable signal is reset and it takes a sequence of three correct triggers before enable is active. for proper operation, the trigger pulse duration must be longer than the input signal debounce time (see item 4.2 in section 7. ?electrical characteristics? on page 9 ) and must not exceed the maximum duration of 45 clock cycles (see item 4.4 in sec- tion 7. ?electrical characteristics? on page 9 ). figure 3-3. pulse diagram of a correct trigger sequence during the short watchdog time v dd re s et o u t mode trigger pin 2 pin 3 pin 5 pin 6 t 0 t 1 t 2 t 3 v dd re s et o u t mode trigger en ab le pin 4 pin 2 pin 3 pin 5 pin 6 t trig t 0 t 1 t 2 t 3 t 2
7 9145d?auto?05/10 ATA5021 3.6 microcontroller in sleep mode 3.6.1 monitoring with the ?long? trigger window the long watchdog mode allows cyclical wake-up of the microcontroller during sleep mode. as in short watchdog mode, there is a disable time, t 4 , and an enable time, t 5 , in which a trigger sig- nal is accepted. the watchdog can be switched from the short trigger window to the long trigger window with a ?high? potential at the mode pin (pin 3). in contrast to the short watchdog mode, the time periods are now much longer and the enable output remains inactive so that other com- ponents can be switched off to effect a further decrease in current consumption. as soon as a wake-up signal at the wake-up input (pins 1) is detected, the long watchdog mode ends, a reset pulse wakes-up the sleeping microcontroller and the normal monitoring cycle starts with the mode switch-over time. figure 3-4 shows the switch-over from the short to the long watchdog mode. the wake-up signal during the enable time, t 5 , activates a reset pulse, t 6 . the watchdog can be switched back from the long to the short watchdog mode with a low poten- tial at the mode pin (pin 3). figure 3-4. pulse diagram of the long watchdog time 3.7 reset-out, pin 5 the reset-out pin functionality is guaranteed for supply voltage down to 1v. in case of a voltage drop, the microcontroller gets a reset up to that value. re s et o u t w a ke- u p mode trigger en ab le pin 4 pin 2 pin 3 pin 1 pin 5 t 2 t 1 t 6 t 4 t 5
8 9145d?auto?05/10 ATA5021 4. state diagram the kernel of the watchdog is a finite state machine. figure 4-1 shows the state diagram with all possible states and transmissions. many transmissions are controlled by an internal timer. the numbers for the time-outs are the same as on the pulse diagrams. figure 4-1. state diagram of the finite state machine s hort window en ab le s t a te s hort window di sab le s t a te long window di sab le s t a te long window di sab le s t a te 2. wedge i s the detection of a s ign a l edge on the w a ke- u p pin a fter the de b o u cing time 3 . trg_ok i s v a lid for once cycle a fter the ri s ing edge on trg_d 4. trg_err i s v a lid if the low period of trg_d i s too long 1. mode_d a nd trg_d a re the de b o u nced s ign a l s of the mode a nd trg pin s note s : re s et o u t s t a te mode s witch s t a te re s et s t a te time-o u t t 0 mode_d = 0 mode_d = 1 mode_d = 1 mode_d = 0 mode_d = 0 trg_ok trg_d = 0 or wedge trg_ok trg_d = 0 time-o u t t 2 time-o u t t 3 or trg_err time-o u t t 5 or trg_err or wedge time-o u t t 4 time-o u t t 1 time-o u t t 6
9 9145d?auto?05/10 ATA5021 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters pin symbol min. max. unit voltage range on pin vdd v vdd,max ?0.4 +6.5 v voltage range on pins v io,max ?0.4 v vdd + 0.4 v output current i out,max ?2 +2 ma hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) v esd,hbm 2 kv ambient temperature range t amb ?40 +125 c storage temperature range t sto ?55 +150 c 6. thermal resistance parameters symbol value unit thermal case resistance junction ambient r thja 180 k/w 7. electrical characteristics v vdd = 5v, t amb = ?40c to +125c, reference point is pin 7, unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* power supply 1.1 current consumption v vdd = 5v r 1 = 66 k c 1 = 470 pf 6i vdd 25 a a 1.2 power-on-reset release reset state with rising supply voltage 6v por1 3.9 4.5 v a 1.3 get reset state with falling supply voltage 6v por2 3.8 4.4 v a 1.4 por hysteresis 6 v por,hys 40 200 mv a 1.5 reset level for low v dd v vdd = 1v to v por1 i rto = 300 a 5v rst 0.1 v vdd a inputs 2.1 logical ?high? v vdd = 5v 1, 2, 3 v ih 3.4 v a 2.2 logical ?low? v vdd = 5v 1, 2, 3 v il 1.6 v a 2.3 hysteresis v vdd = 5v 1, 2, 3 v in_hys 0.6 1 1.4 v a 2.4 pull-down current v in = 5v v vdd = 5v 1i pd 520aa 2.5 pull-up current v in = 0v v vdd = 5v 2, 3 i pu ?20 ?5 a a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. frequency deviation also depends on the tolerances of the external components 2. cycle = period of clock frequency (see section 3.2 on page 4 )
10 9145d?auto?05/10 ATA5021 outputs 3.1 maximum output current 4, 5 i out ?2 +2 ma c 3.2 logical output ?low? i out = 1 ma 4, 5 v ol 0.2 v a 3.3 logical output ?high? i out = ?1 ma 4 v oh v vdd ? 0.2 va 3.4 leakage current v out = 5v 5 i leak 2aa timing 4.1 frequency deviation (1) r 1 = 66 k c 1 = 470 pf v vdd = 4.5v to 5v (2) 8f dev 5%c 4.2 debounce time 2,3 t deb1 3 4 cycle d 4.3 1 t deb2 96 128 cycle d 4.4 maximum trigger pulse length 3t trgmax 45 cycle d 4.5 power-up reset time t 0 201 cycle d 4.6 switch-over mode time t 1 1112 cycle d 4.7 disable time short watchdog window t 2 130 cycle d 4.8 enable time short watchdog window t 3 124 cycle d 4.9 disable time long watchdog window t 4 71970 cycle d 4.10 enable time long watchdog window t 5 30002 cycle d 4.11 reset-out time t 6 40 cycle d 7. electrical characteristics (continued) v vdd = 5v, t amb = ?40c to +125c, reference point is pin 7, unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. frequency deviation also depends on the tolerances of the external components 2. cycle = period of clock frequency (see section 3.2 on page 4 )
11 9145d?auto?05/10 ATA5021 9. package information 8. ordering information extended type number package remarks ATA5021-tapy so8 taped and reeled, pb-free, small reel ATA5021-taqy so8 taped and reeled, pb-free, big reel package: so 8 dimensions in mm specifications according to din technical drawings issue: 1; 15.08.06 drawing-no.: 6.541-5031.01-4 14 85 0.2 5 0.2 3.8 0.1 6 0.2 3.7 0.1 4.9 0.1 3.81 0.4 1.27 0.1 +0.15 1.4
12 9145d?auto?05/10 ATA5021 10. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 9145d-auto-05/10 ? section 3.2 ?rc oscillator, pin 8? on pages 4 to 5 changed 9145c-auto-09/09 ? section 3.2 ?rc oscillator, pin 8? on page 4 changed ? el. char. table: rows 3.1, 3.2, 3.3 changed 9145b-auto-05/09 ? put datasheet in the newest template ? section 3.2 ??rc oscillator, pin 8? on pages 4 to 6 updated ? section 3.5 ?microcontroller in active mode? on page 7 updated ? section 7 ?electrical characteristics? numbers 1.1 and 4.1 on pages 10 to 11 updated
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